PCB Stackup Planning for Controlled Impedance

List every controlled net: single-ended values, differential pairs, and any coplanar structures. Note which layers they must route on and whether they share reference planes with power or ground. Layer count follows from plane assignment and routing density—not the other way around.

On a four-layer board, the classic signal–ground–power–signal arrangement gives every outer-layer trace one solid reference and works for most 50 Ω single-ended and 100 Ω differential requirements. Six layers buys either two stripline routing layers between planes or better power integrity; which one you need depends on the net list you just wrote. Jumping straight to “we always build eight layers” is how designs end up paying for laminations that solve nothing.

If a high-speed link spans connectors, include the connector launch geometry in the discussion. A perfect mid-board pair that degrades at the launch still fails system tuning. The same applies to AC-coupling capacitor pads and test points sitting in the middle of a controlled run: every discontinuity belongs in the plan, not in the debug session.

Microstrip places the signal on an outer layer with a reference plane on the next inner layer—easy to route, more exposed to surface finish and environmental variation. Stripline sandwiches the signal between two reference planes—harder to access for probing, but more stable for tight tolerance and longer runs.

The exposure difference is not academic. Outer-layer traces are affected by solder mask thickness (which lowers impedance by a few ohms), by the finish (ENIG nickel adds loss at high frequency), and by the etched trace’s trapezoidal cross-section. Inner stripline traces see none of this—one reason tight-tolerance nets and long backplane runs usually live inside the board while short breakouts and antennas live on the surface.

Coplanar waveguide adds lateral ground on the same layer; include ground gap in the table when you use it. Fabricators cannot infer coplanar geometry from trace width alone.

For each layer: name, copper weight, dielectric material and thickness to the next layer, and overall board thickness target. For each controlled structure: target ohms, tolerance, trace width and gap if fixed, and reference layer IDs.

Material callouts deserve precision. “FR-4” spans laminates whose dielectric constant ranges roughly from 3.8 to 4.8 depending on resin content and glass style—and Dk varies with frequency, so state the frequency your targets were calculated at. If the fabricator needs to substitute an equivalent laminate (common when your named material is not stocked), the table gives them enough information to re-solve trace geometry and come back with a proposal instead of a silent change.

State whether impedance is calculated with solder mask included or excluded—outer-layer microstrip disagreements often start here. If you need ±7% or ±5%, say so in the RFQ; default assumptions are usually ±10% on standard FR-4. Above roughly 10 GHz, also discuss copper foil roughness: standard electrodeposited foil adds measurable conductor loss that smooth-foil laminates exist to solve.

The most common failure is a reference-plane crossing: a controlled trace routed over a split or a plane cutout loses its return path, and no stackup table fixes what layout broke. Second is the assumption that the CAD tool’s default dielectric table matches what the fabricator will actually press—tool defaults are generic; real laminate menus are discrete. Third is asymmetric copper distribution that forces the shop to rebalance the stackup for warp control, changing the dielectric spans your calculation depended on.

Less obvious: trace-width changes at connector launches and BGA breakouts. A 50 Ω trace that necks down to escape a fine-pitch field is briefly a different impedance; over short distances this is usually acceptable, but it should be a decision, not an accident. During stackup review we flag these transitions when the routed data is available—one more reason to share layout, not just targets, on impedance-critical programs.

Panelize coupons when the program depends on measured impedance—not simulated hope. Match coupon layer order and materials to the production panel. Specify whether you need TDR reports on first article or on every lot.

A useful coupon carries one trace per controlled structure, long enough for a clean TDR window (typically 100 mm or more), with the same via transitions the production nets use if via launches matter to you. Ask for the raw TDR traces alongside the summary numbers—the trace shape distinguishes a uniform 5% miss (dielectric substitution) from local excursions (etch or registration), which determines whose problem it is and how it gets fixed.

At MOZPCB, impedance tables attached to the first RFQ move quotes faster because CAM does not invent a dielectric set. If targets are still open, mark them TBD and resolve in review—still cheaper than a re-spin.